Abstract
The CMOS rail-to-rail fully differential Opamp has an input stage and a class AB output stage, which can provide both input and output rail-to-rail operations. Its input stage is composed of an NMOS differential pair and a PMOS differential pair. HSPICE simulation results are preformed using level 49 model of a 0.5μm CMOS process. This Opamp has a dc gain of66dB, a unity-gain bandwidth of 2.1MHz and a phase margin of 64°.
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