A CMOS Highly Linear Doherty Power Amplifier With Multigated Transistors

Abstract

This paper presents a highly linear and power back-off efficiency-enhanced Doherty power amplifier (PA) fully integrated into CMOS. The proposed Doherty PA employs a transformer-based quadrature signal generator, multigated transistors (MGTRs) in the main PA, Class-C mode auxiliary PA, and synthesized transformer-based Doherty parallel output network with the second-harmonic control circuits. An on-chip 8-port transformer-based quadrature signal generator is designed within a single transformer footprint ( $340\,\,\mu \text{m}\,\,\times 340\,\,\mu \text{m}$ ) and provides 0°/−90° differential signals to the main/auxiliary PAs. The MGTR in the main PA is implemented using four transistors with different sizes and biases to generate and extend a near-zero $\text {g}_{\text {m3}}$ operation region. Moreover, an on-chip transformer-based Doherty parallel output network with the second-harmonic control circuits shows higher passive efficiency compared with a conventional Doherty parallel output network and provides low second-harmonic loads to the main/auxiliary PAs. Both the proposed MGTR in the main PA and the second-harmonic control circuits in the main/auxiliary PAs suppress the third-order intermodulation distortion of the Doherty PA. This results in a substantial linearity improvement of the Doherty PA, which can support high-order modulation signals and reduce or even eliminate the need for digital predistortion (DPD). As a proof-of-concept design, a 5.8 GHz Doherty PA is implemented in a standard 55 nm bulk CMOS process. The proposed Doherty PA exhibits 27.2 dBm saturated output power with 24.5% power-added efficiency (PAE) at 5.8 GHz. The measured error vector magnitude with 40/80 MHz of 64-QAM/256-QAM is 2.5%/1.8% with 20.7/17 dBm average output power, 9.5%/5.3% average PAE, and −33.2/−36.3 dBc adjacent channel leakage ratio without any DPD.