A CMOS High Speed Multi-Modulus Divider With Retiming for Jitter Suppression

Abstract

A new asynchronous high speed multi-modulus divider (MMD) architecture is presented in this letter. This new architecture significantly reduces the delay of the critical path, which not only pushes to ultra-high speed operation, but also allows retiming techniques to suppress jitter accumulation from the divider chain simultaneously. A prototype in a 65 nm CMOS technology has demonstrated an improved speed over three times compared with a conventional MMD and a reduced phase noise about 8.4 dB due to a retiming scheme. To the authors' best knowledge, this MMD has demonstrated to date the highest operating frequency static MMD with retiming function in CMOS. Due to its static implementation, this MMD can operate from 19 GHz down to close to dc with programmable division ratios from 16 to 31. This MMD consumes 39.8 mW power and occupies 0.011 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area.