A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL

Abstract

A 100MHz-to-5GHz divide-by-16-to-255 multi-modulus divider (MMD) is designed and implemented in TSMC 65nm CMOS technology. It consists of 7 stages of divide-by-2/3 dual-modulus divider connected in cascade with digital control logic circuits. To speed up the operating frequency and achieve the wide-division-ratio, 2 TSPC logics merged with AND gate are adopted, which can also save the chip area and power dissipation. The MMD works properly from 100MHz up to 5GHz with programmable division ratios from 16 to 255. The power consumption of the whole divider is about 3.95 mW under a supply voltage of 1.2 V with 5 GHz input frequency and chip size is 205×96 um2.