Abstract
A CMOS-compatible complementary SINFET (Schottky injection field effect transistors) process is described. The high speed n- and p-channel SINFETs use Schottky-barrier injectors to provide higher current handling capability than presently available in a CMOS-compatible HVIC environment. Schottky-barrier height enhancement implants are used to optimize the injection level in the SINFETs n- and p-buried layers which are used for breakdown control and isolation. Low-voltage CMOS control circuits and complementary merged MOS-bipolar output devices with current sourcing and sinking capabilities can be fabricated using the process. >
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