A CMOS charge preamplifier for silicon drift detectors with on-chip JFET and feedback capacitor

Abstract

In the framework of the Silicon Drift Detector for Hadronic Atom Research by Timing Application (Siddharta) project, we are developing the CMOS readout electronics for the analog processing of about 200 large-area (1 cm 2) silicon drift detectors (SDDs). The readout electronics have to provide an energy resolution better than 150 eV at 6 keV, when used with SDDs, and high long-term peak stability, in the order of few eVs, with respect to background variations during the experiment. The high-stability requirement imposes the choice of a charge preamplifier configuration as front-end stage. In our case, the peculiarity of the preamplifier is that the input JFET and the feedback capacitor are integrated in the detector chip, separated by the remaining part of the circuit, which is several centimeters away. In this work we describe a CMOS charge preamplifier designed to meet these specific constraints and characterized by the use of a drain feedback technique for the reset of the leakage current and signal charge. To this aim, a low-frequency loop is designed to actively control the drain of the SDD–JFET with full compatibility with the supplies limits of the CMOS technology. Because of the unpredictable value of the feedback capacitor, the circuit foresees the possibility to externally adjust the preamplifier decay time to achieve the correct pole-zero compensation with the fixed zero of the shaping amplifier. The main features of the circuit, as well as the results of the experimental characterization of a first prototype realized in the 0.35 μm CMOS AMS technology, are presented in the paper.