Abstract
Defectivity is another critical aspect of Chemical Mechanical Planarization (CMP) processing and other than typical CMP induced defects: micro scratches, slurry particles, etc., there are other types of critical wafer defects that negatively impact process yields in Nano semiconductor process manufacturing. A case of an observational study draws that in comparison to reference levels, wafer functional yields were lower than expected. In result, defective chips were displayed an Electro-Static Discharge (ESD) breakdown issue in the common Metal Interconnect induced damage during Chemical Mechanical Polishing. This paper describes the CMP process module partitioning and tool charging analysis pointed out by the specific unit of the Applied Materials Mirra-Mesa CMP tool of HCLU (Head Clean Load/Unload) at the post inter-metal dielectric (IMD) chemical mechanical polishing (CMP) step [1–2]. This work is focused on the defects generated by the present Electrostatic Discharge (ESD) resistivity specified at limits of de-ionized water (DIW) that induced electrostatic damage during Chemical Mechanical Planarization. To eliminate such ESD breakdown, we provide a design of experiments (DOE) which complements efficiently what is possible with existing extraction tools. Through the proposed DOE set, charging induced damage (CID) into common metal interconnect have been analyzed and evaluated.
Published Version
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