A Benchmark Study of Complementary-Field Effect Transistor (CFET) Process Integration Options Done by Virtual Fabrication

B Vincent,J Boemmels,J Ryckaert,J Ervin

doi:10.1109/jeds.2020.2990718

Abstract

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanosheet stacked channels provided superior process integration robustness compared to Nanowire-On-Fin stacked channels. For the Nanowire-On-Fin option, using an SOI substrate as the starting material (compared to Si bulk or DSOI) also strongly reduced process variation failure rates.

Highlights

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real estate limitations at this increased device density
We use the terms “Fin” to denote a vertical sheet of Silicon in contact with the Si substrate, “Nanowire” a vertical sheet of Silicon isolated from the Si substrate, and “Nanosheet” a horizontal sheet of Silicon isolated from the Si substrate
The Double Silicon-On-Insulator (DSOI) option differs from the SOI case by using one additional BOX layer to isolate the bottom transistor from the substrate

Summary

Introduction

Sub-5 nm logic nodes will require an extremely high level of innovation to overcome the inherent real estate limitations at this increased device density. Each process flow studied had a specific channel architecture (Fin, nanowire or nanosheet) and a specific process flow with different Si starting substrates: bulk, Silicon-On-Insulator (SOI) [5], or Double Silicon-On-Insulator (DSOI) [6].

Results

Conclusion