Abstract
In this work, we demonstrated 3D sequential complementary field-effect-transistor (CFET) by direct wafer bonding (DWB) technique and a low-temperature process for monolithic 3D(M3D) integration using a high-performance top Ge (110)/<110> channel on bottom Si CMOS. Here, the maximum thermal budget was up to 400°c during the fabrication of top Ge FET, allowing high-performance heterogenous Ge/Si CFET without damage to bottom Si FETs. Furthermore, we systematically investigated the mobility enhancement to channel orientation in thin Ge (110) nanosheet channel pFET. Low effective hole mass along <110> direction on Ge (110), which was calculated by the k$\cdot$p method, provided record high mobility of approximately 400 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V$\cdot$ s (corresponds to 743 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V$\cdot$ s when normalized by footprint) among the reported Ge pFET with similar channel thicknesses at room temperature.
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