A 95fJ/b current-mode transceiver for 10mm on-chip interconnect

Abstract

Data communication between local system blocks through on-chip global interconnects presents significant design challenges in scaled VLSI systems. The goal of this research is to reduce the energy consumed per bit transmitted, while achieving Gb/s data rates over interconnect lengths up to 10mm. Voltage-mode signaling with capacitive boosting [1-2] has been proposed for low-power on-chip interconnects. To increase the data rate over RC-limited interconnect, aggressive equalization schemes should be used in receivers [1-3] and transmitters [1-2] at the cost of significant power consumption. As an alternative to voltage-mode signaling, current-mode signaling has been considered. It was originally used for fast bitline sensing in memory [4-5] to take inherent advantage of a reduced RC time constant. However, prior work on current-mode transceivers for on-chip interconnect shows worse energy efficiency than their voltage-mode counterparts due to large static power dissipation by current-sensing circuit [6-7]. This paper presents a 95fJ/b current-mode transceiver for on-chip global interconnect. The transceiver is implemented in 65nm CMOS and achieves a data rate of up to 4Gb/s over a 10mm link with a BER of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> .