Abstract
In this paper, a 5-GHz frequency synthesizer based on sub-sampling phased locked loop (SSPLL) using a pulse-width to current conversion (PWCC) circuit is presented. The proposed PWCC technique converting the pulse-width of input clock signal into a modulated output current is applied to improve the conventional sub-sampling phase detector and charge-pump. Implemented by 180 nm CMOS process, the proposed frequency synthesizer dissipates 15.52m W from a 1.8- V power supply. The operation frequency is from 4.7 GHz to 5.2 GHz under the channel width of 10 MHz. The measured output spurious tone is −45.7 dB and the phase noise performance is −128.22 dB/Hz at 10 MHz offset.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
