A 57-64 GHz Two-Way Parallel-Combined Power Amplifier with 16.6 dBm Psat and 23.6% Peak PAE in 40nm Bulk CMOS

Abstract

This paper presents an efficient and linear two-way parallel-combined CMOS power amplifier (PA). A pair of over-neutralization cross-coupled capacitors are used to boost the power gain and ensure stability. Design-oriented analysis leads to the optimum efficiency of the transformers in the power combiner, and the dummy-shielding winding is applied to improve the load impedance uniformity seen by each PA cell. Fabricated in a 40 nm CMOS process, the P A achieves 23.6 % peak power added efficiency (PAE), 16.6 dBm saturated output power $\left(P_{\text {sat }}\right)$, and 14.6 dBm output 1-dB compression point $\left(\mathrm{P}_{1dB}\right)$ with 20.5 % PAE. The peak PAE is above 20 % and $P_{\text {sat }}$ is above 15 dBm across 57-64 GHz frequency range. P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf> exceeds 14 dBm from 59 GHz to 64 GHz.