A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS

Abstract

This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA drivers and segments are switched on and off according to signal power; thus, the PA power consumption correlates with the power of the input signal. Binary power gain variations due to PA segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the tradeoffs between power efficiency and linearity by employing the digital predistortion technique. The PA is implemented in a 40 nm CMOS process. It delivers a saturated output power of 35 dBm with 44.9% peak power-added efficiency (PAE) and a linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at $\pm {5}\;\text{MHz}$ at a maximum linear output power of 31 dBm for a baseband WCDMA signal is $- {35}.{8}\;\text{dBc}$ .