A 50–64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology

Abstract

This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the delay line and the output combiner by applying the design methodology of LC-ladder filters. Proper arrangement of the output combiner reduces the required number of inductors and hence reduces the area. In addition, a novel 4:1 multiplexer (MUX) is used as the final stage of the serializer to reduce power. Designed and fabricated in 65 nm CMOS technology, the transmitter achieves a maximum data rate of 64.5 Gb/s with an energy efficiency of 3.1 pJ/bit.