Abstract
A novel 8Gbps, 4:1 transition aware multiplexer (MUX) is proposed. The multiplexer core is basically a self-toggling TSPC flip-flop, which is deactivated when no data transition is detected. The high speed serial data is regenerated by gating the triggered clock. It combines the advantages of data retiming to eliminate deterministic jitter. Besides, the short clock-to-Q b delay enables high speed multiplexing. Power reduction can be achieved by deactivating the power hungry flip-flop thanks to the random probability of data transition. Fabricated in 55 nm CMOS technology, the core circuit occupies a chip area of 77 × 81μm2 only. It dissipates 10.3 mW from a 1.2 V supply.
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