A 5-bit 4.2-GS/s Flash ADC in 0.13-.MU.m CMOS Process

Abstract

This paper investigates and analyzes the resistive averaging network and interpolation technique to estimate the power consumption of preamplifier arrays in a flash analog-to-digital converter (ADC). By comparing the relative power consumption of various configurations, flash ADC designers can select the most power efficient architecture when the operation speed and resolution of a flash ADC are specified. Based on the quantitative analysis, a compact 5-bit flash ADC is designed and fabricated in a 0.13-µm CMOS process. The proposed ADC consumes 180mW from a 1.2-V supply and occupies 0.16-mm2 active area. Operating at 3.2GS/s, the ENOB is 4.44bit and ERBW 1.65GHz. At 4.2GS/s, the ENOB is 4.20bit and ERBW 1.75GHz. This ADC achieves FOMs of 2.59 and 2.80pJ/conversion-step at 3.2 and 4.2GS/s, respectively.