A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5–11.5 Gb/s Serial Links

Abstract

This paper presents the design of a power- and area-efficient, high-performance dual-path receiver analog front-end (AFE) for wide multistandard applications of 8.5–11.5 Gb/s, such as 10GBASE-LRM, 10GBASE-KR, 10GBASE-CX1, and 10GBASE-LR/SR. A common programmable gain amplifier (PGA) with programmable peaking is followed by ADC-based and slicer-based paths. The ADC-based path employs a low-power, 6-bit 10 Gs/s, 4X time-interleaved, low BER rectified flash 10 Gs/s ADC that is digitally calibrated to compensate for offset, gain, and phase mismatches between the interleaved channels. The ADC-based receiver with transmitter can compensate for up to a 34 dB insertion loss at 5 GHz Nyquist frequency for a copper backplane channel (10GBASE-KR). The ADC-based receiver can achieve greater than 6 dB margin for three 10GBASE-LRM stressors and dynamic channels. The ADC Figure of Merit (FoM) is a 0.59 pJ/conversion-step for a 5 GHz input at a 10.3125 GHz clock rate. The slicer-based path uses a continuous-time linear equalizer (CTLE) after high linear PGA to provide 10 dB total equalization at 5 GHz Nyquist frequency for 10GBASE-SR application. Its measured input sensitivity of 30 mVppd and high-frequency jitter tolerance of 0.35 UIpp with 0.7 UIpp total input jitter well exceed specifications in the standard. The receiver AFE occupies 0.82 mm 2 and consumes 195 mW for ADC path and 55 mW for slicer path in a 40 nm standard CMOS process.