An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS

Abstract

This paper presents the design of an inverter-based analog receiver front-end (AFE) that was evaluated within a complete ADC-based 56 Gb/s PAM4 wireline transceiver system. The front-end contains hybrid continuous-time linear equalizers (CTLE) with low- and high-frequency peaking as well as inverter-based programmable gain amplifiers (PGA) that serve as T/H buffers for the 32x time-interleaved SAR ADC. The inductorless design achieves high bandwidth through a reduced number of equalizer stages (with fewer parasitic poles) and active peaking techniques. The transceiver that contains the AFE achieves <;10- <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> BER over a backplane channel with 35 dB loss at 14 GHz with 2 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> input crosstalk noise. The AFE core occupies 0.00425 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in 16 nm FinFET CMOS and consumes 165 mW.