Abstract
This letter presents a low-power, 40-Gb/s optical receiver front-end fabricated in a 65-nm CMOS technology. Using an inverter-based topology for both the transimpedance amplifier and the post amplifier, high energy efficiency has been obtained. Cascaded amplifiers with transconductance and transimpedance combinations are utilized to acquire a bandwidth of 29.6 GHz. A low-dropout voltage regulator is applied to reduce the supply noise of the single-ended amplifiers. The prototype chip excluding output buffer consumes only 12.4 mW (310 fJ/b) at a 1.2 V single supply, and the integrated input referred noise is 9.2 $\mu \text{A}_{\mathrm { {rms}}}$ .
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