Abstract
An ultra-high speed 1bit full adder based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology is presented. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce the power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350mW.
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