Abstract
SRAM scaling faces increasing challenges in meeting power, performance, and density requirements as Moore's law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologies and conventional SRAM is no longer able to fully realize the benefits of scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. VCC scaling is especially important to meet increasingly stringent power constraints [1]. Circuit techniques proposed in recent years enable SRAM V CC scaling by expanding read and write margins [2–6]. However, the improved design margins for SRAM V CC scaling are often achieved with significant design overhead, e.g., additional power supply [4], increased circuit complexity [5], and testing overheads required for die-by-die programming [6].
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call