A 32 b microprocessor with on-chip 2 K byte instruction cache: M Horowitz, J L Hennessy, P Chow, P G Gulak, J M Acken, A Agarwal, C Chu S A McFarling, S A Przybylski, S Richardson, A Salz, R T Simoni, D C Stark, P Steenkiste, S W K Tjang, M J Wing (Stanford Univ. Center for Integrated Syst., CA,

doi:10.1016/s0026-2692(88)80164-2

A 32 b microprocessor with on-chip 2 K byte instruction cache: M Horowitz, J L Hennessy, P Chow, P G Gulak, J M Acken, A Agarwal, C Chu S A McFarling, S A Przybylski, S Richardson, A Salz, R T Simoni, D C Stark, P Steenkiste, S W K Tjang, M J Wing (Stanford Univ. Center for Integrated Syst., CA,

https://doi.org/10.1016/s0026-2692(88)80164-2

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Journal: Microelectronics Journal

Publication Date: Sep 1, 1988

#International Solid State Circuits Conference #IEEE International Solid State Circuits + Show 8 more

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A 32 b microprocessor with on-chip 2 K byte instruction cache: M Horowitz, J L Hennessy, P Chow, P G Gulak, J M Acken, A Agarwal, C Chu S A McFarling, S A Przybylski, S Richardson, A Salz, R T Simoni, D C Stark, P Steenkiste, S W K Tjang, M J Wing (Stanford Univ. Center for Integrated Syst., CA,

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