Abstract
A pipelined 32 b microprocessor with 13 kB of cache memory: A Berenbaum (AT&T Inf. Syst., Holmdel, NJ, USA), B W Colbry, D R Ditzel, R D Freeman, H R McLellan, M Shoji, K J O'Connor 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA:
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