A $2.8\mu \mathrm{A}$, sub-$1\mu \mathrm{s}$ Output-Capacitorless LDO with Transient Detecting Control Technique

Abstract

In this paper, a low power and fast transient response output-capacitorless LDO for digital applications is implemented in a <tex>$0.18-\mu\mathrm{m}$</tex> standard CMOS technology. An adaptive biasing class-AB amplifier circuit is proposed to provide both high gain and large slew rate with low quiescent current. Meanwhile, a push-pull slew rate enhance stage controlled by transient detecting control (TDC) generator is proposed to further improve the transient response of the proposed LDO. Simulation results show that the quiescent current is only <tex>$2.8\mu\mathrm{A}$</tex>. And the settling time of the output voltage when the load current steps from 1mA to 100mA with an edge time of 1ns is less than <tex>$2\mu\mathrm{s}$</tex>. Moreover, the line regulation and load regulation are O.69mV/V and <tex>$2.4\mu\mathrm{V}/\text{mA}$</tex>, respectively.