Abstract
This paper presents a low quiescent current, fast transient response output capacitor-less LDO implemented in a 180nm standard CMOS technology. A dynamic slew rate enhance buffer with transient spike detecting is proposed to improve the load transient response. Besides, a low power class-AB amplifier with gain enhance transistors is used to keep high loop gain for good regulated performance. According to the simulation result, the quiescent current of the LDO is only 283nA. Meanwhile, when the load current steps from 1 mA to 15 mA with a 300-ns edge time and a 0-pF output capacitor, the transient ripple is only 141.9 mV. Besides, the line regulation is only 0.305 mV/V and the load regulation is only 17.79 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu \mathbf{V/mA}$</tex> .
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