Abstract
This paper presents the design and characterization of a low output jitter and high resolution pulsewidth modulator in 45-nm SOI CMOS. The modulator uses a current mode logic (CML) delay line to generate delayed phases of a reference signal. A digital input vector selects a particular delayed phase inside a CML phase selector. The delayed and undelayed phases of the reference are then combined inside a CML OR gate to generate different pulsewidths. The designed 2-bit 10 Gb/s CML pulsewidth modulator offers the highest time resolution of 10 ps, least output jitter of 0.6 ps, and among the best energy figures of 2.8 p.J/bit in comparison to the reported pulsewidth modulators.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call