A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOS

Abstract

In this work, we propose a half-rate 2^7-1 pseudo random bit sequence(PRBS) generator by employing highly power efficient charge-mode circuit topology at 16-Gb/s. At the target data-rate, proposed charge-mode implementation have the lowest power consumption compared to the traditional currentmode PRBS generator implementations, thanks to the availability of high speed switches in sub-100nm technologies. The proposed charge-mode half-rate PRBS generator is implemented in 1.2 V, 65-nm CMOS technology with a power consumption of 3.35 mW, timing jitter of 0.2 ps and FoM of 0.02-pJ/bit at 16-Gb/s. Thus, the proposed power efficient charge-mode implementation of PRBS generator is an attractive candidate for on-chip biterror-rate(BER) test and measurement applications.