A 2×2 80 Gbps 215-1 PRBS generator with three operational modes and a clock divider

Abstract

An 80 Gbps 215-1 pseudo-random bit sequence (PRBS) generator offering a unique feature of two programmable channels is presented. It is possible to select either a replica of the full rate stream, two parallel streams at half the rate, or a combination of external and internal pattern to the output. This flexibility makes the design suitable for generating proper test signal for both binary and 4-PAM (pulse-amplitude-modulation) communication systems. While the longer sequence in this design adds to the complexity, the energy per bit is comparable with the state-of-the-art designs. Notably for the clock drivers, as one of the bottlenecks of a PRBS generator, an open-collector structure with distributed loading is studied and optimized for very low power operation. The design features a clock divider and zero detection circuit as well. The circuit was fabricated in a 130 nm SiGe BiCMOS process (300/500 GHz fr/fmax).