Abstract

A 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> -1, 80Gb/s pseudo-random bit sequence (PRBS) generator, employing parallel architecture is presented. The generator is optimized to provide a high bit rate as well as a long sequence length without any need of inductive peaking for a lower power consumption, compared to PRBS generators reported in literature. The PRBS generator consists of two parallel complementary rows of linear feedback shift registers (LFSR), operating up to 40Gb/s, where the generated PRBS from each are multiplexed to provide a bit-rate of double the clock frequency, reaching up to 80Gb/s. The clock distribution network was carefully optimized for a reduced amplitude and phase error to push the boundaries of the maximum achievable bit-rate. The PRBS generator is capable of generating bit-rates ranging from 10Gb/s up to 80Gb/s, with a power consumption of 576 mW to 1 W. The circuit is manufactured in an 0.35 μm SiGe-Bipolar technology with an f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> of 200 GHz.

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