Abstract
This article proposes a fractional- N digital phase-locked loop (DPLL) that achieves a 265- $\mu \text{W}$ ultra-low-power operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked- $g_{m}$ oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional- ${N}$ DPLL consumes only 265 $\mu \text{W}$ while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB.
Highlights
T HE demand for ultra-low-power (ULP) circuits and systems has exponentially increased with the growth of today’s system-on-chip (SoC) devices
Even though the lock-in range is enhanced by the proposed switching feedback and the ODZ detector, the digital phase-locked loop (DPLL) may still be trapped in incorrect lock-in ranges
A coarse to-digital converter (TDC) is inserted after the phase-frequency detector (PFD) of the ODZ detector to quantize the coarse phase error and assist with coarse phase and frequency locking through the 11-bit coarse bank of the digitally controlled oscillator (DCO) [2]
Summary
T HE demand for ultra-low-power (ULP) circuits and systems has exponentially increased with the growth of today’s system-on-chip (SoC) devices. A DTC is used to shrink the required TDC range to lower power consumption The operation of this architecture is very similar to that of the analog sub-sampling PLL, which uses a reference to directly sample the oscillator output [17]–[20]. A DPLL [21] based on this architecture achieved a very low power consumption of 0.67 mW with a jitter of 1.98 ps and an in-band fractional spur of −56 dBc. The key challenges for furthering reducing power consumption are: 1) reducing the power consumption of the building blocks operating at the oscillator frequency and 2) reducing the power consumption from the DCO while maintaining a large output swing and a low phase noise. The obtained power consumption is nearly 2.5 times smaller than that of a state-of-the-art low-power fractional-N DPLL [2]
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