A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration

Abstract

A 2.5 GS/s12-bit 4-channel time-interleaved SAR-assisted pipelined ADC is proposed. The bias-enhanced ring amplifier serves as a residual amplifier offering high bandwidth and superior power efficiency over conventional operational amplifier. A high linearity front-end is proposed to mitigate the non-linearity of the ESD diode and provide sufficient driving ability. In addition, it can reject the kickback noise from the core ADC. A digital background calibration method with digital-mixing is adopted to fix the mismatches among channels. The measured SNDR/SFDR with a low-frequency of the prototype ADC are 51.0/68.0 dB, achieving a competitive FoM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</inf> of 0.48 pJ/conv.-step at 2.5 GS/s.