A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

Jingchao Lan,Zhekan Ni,Junyan Ren,Xingchen Shen,Fan Ye,Danfeng Zhai,Yongzhen Chen

doi:10.3390/electronics10243173

Jingchao Lan, Zhekan Ni + Show 5 more

Open Access

https://doi.org/10.3390/electronics10243173

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Abstract

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

Highlights

We explore a pipelined successive approximation register (SAR) architecture as the channel analog-to-digital converter (ADC) to achieve a balance between channel number and power consumption
The time-interleaved ADC (TI-ADC) is clocked from an external low-noise signal generator, and the four-phase divided clock after the global clock generator is distributed to the channel ADC symmetrically, as Figure 6 shows
The input signal is generated from a signal source (Agilent E8267D), followed by a band-pass filter with a center frequency equal to the input frequency to guarantee the spectrum purity

Summary

Introduction

High-speed ADC (fs ≥ 1 GHz) plays an essential role in broadband communication systems, such as high-speed digital oscilloscopes, base-station, direct RF receivers, and software-defined radio [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24]. The mismatches between channel ADCs would deteriorate the performance of the TI-ADC, especially when the input frequency increases. These mismatches include offset, gain, bandwidth, and timing errors. In [10], a reference ADC (slow, yet accurate) for background calibration is proposed to correct the timing mismatch based on the same input signal is sampled and quantified by the reference ADC and under-calibrated channel ADC. A statistics-based [11] fully digital background method is proposed using the Taylor series approximation for error calibrations.

Ring Amplifier Review

TI-ADC Architecture

FIFO Details

Digital Background Calibration

Measurement Results

Conclusions