Abstract
This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ƒt of 175GHz and a peak ƒmax of 260GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/−0.07 LSB and +0.27/−0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7dB for a sinusoidal output of 72.5MHz at a sampling rate of 13.5GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24GS/s are also obtained. The total power consumption is as low as 0.88W with a supply voltage of −4.0V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5bits or more.
Published Version
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