A 230-MHz half-bit level pipelined multiplier using true single-phase clocking

Abstract

An 8-bit*8-bit signed two's complement pipelined multiplier megacell implemented in 1.6- mu m single-poly, double-metal N-well CMOS is described. It is capable of throughputs of 230,000,000 multiplications/s at a clock frequency of 230 MHz, with a latency of 12 clock cycles. A half-bit level pipelined architecture, and the use of true single-phase clocked circuitry are the key features of this design. Simulation studies indicate that the multiplier dissipates 540 mW at 230 MHz. The multiplier cell has 5176 transistors, with dimensions of 1.5 mm*1.4 mm. This multiplier satisfies the need for very high-throughput multiplier cores required in DSP architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>