Dual signal configuration for low power low voltage high performance pipeline multiplier

Abstract

A multiplier cell using dual signal configuration has been used for high performance low power low voltage pipeline multiplier. The proposed configuration requires less pipelining buffers; hence, achieving higher efficiency in terms of power consumption and silicon area. The multiplier cell is synchronized with the relocated clocked buffers which are operated with a non-overlapping two-phase clock. Simulation results showed that the proposed circuit delivered two times the throughput and half the pipeline latency of implementations with better power consumption.