A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time

Abstract

In ultra deep submicron technologies the process variation makes a vital impact on the design. The favorable device characteristic of FinFET avails them as a popular contender for a replacement of CMOS technologies. An optimal approach to increase the access time of a 6T-SRAM cell based on 22 nm FinFET technology is presented in this paper. The approach considers the statistical variation of supply voltage (Vdd) and their corresponding access time variation (read and write) due to technological transform. The spice code is developed and analyzed using HSPICE EDA tool. The simulation results of the read and write access time are evaluated using HSPICE and with Custom WaveView. The results show 11.057 and 12.233 ps for read and write access time at Vdd = 0.80 V which is the nominal voltage for 22 nm FinFET. The power consumption of the 6T-SRAM cell based on the proposed technique is 0.140 mW (at Vdd = 0.80 V) which is explored using Monte Carlo simulation in HSPICE.