Abstract
This paper present a receiver front-end (hereinafter referred to as receiver) that supports NRZ and PAM4 signaling. It includes an analog frontend (AFE) and a decision feedback equalizer (DFE). The AFE consists of a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA) and a buffer. Careful budget is planned to deal with received signal which come through a channel with up to 20dB insertion loss (IL). Several techniques are adopted to improve its bandwidth. The receiver is fabricated in 65nm CMOS process and its core area is 0.34mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show that the receiver could work at 20Gbuad. It draws 167mA from 1V power supply. Finally, the circuit optimizations are discussed according to the experiment.
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