Abstract
A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained.
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