A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Abstract

This brief describes a wide-range operating false-lock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.