Investigation of experimental verification for various Power Distribution Network cases through DLL Clock jitter affected by SSN

Abstract

Delay Locked Loop (DLL) is essential circuit to design the low jitter synchronous transceiver system. One of the important performance factors on DLL is amount of clock jitter. Output clock jitter of DLL is affected by several noise sources including Simultaneous Switching Noise (SSN) from external circuit. SSN voltage becomes large portion and critical factor of analog circuit noise in mixed and complicated system. It is difficult to express the relation between SSN voltage and output clock jitter through numerical equation. SSN-to-jitter transfer function will be an effective estimation method for DLL output clock jitter. This transfer function means ratio of SSN voltage to output clock jitter on DLL circuit at each frequency. To obtain the SSN-to-jitter transfer function need to consider both circuit characteristic and Power Distribution Network impedance. In this paper, we present how to acquire the SSN-to-jitter transfer function on DLL considering PDN and investigate the changed transfer function depend on various PDN cases. Obtained SSN-to-jitter transfer function will be verified by measurement result.