A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration

Abstract

This brief presents a two-channel 14-bit 500-MS/s time-interleaved analog-to-digital converter (ADC) with background time skew calibration fabricated in a 0.18- ${\mu }\text{m}$ CMOS process. Time skew is detected with an improved autocorrelation-based strategy and corrected with digitally controlled delay line. Different from traditional strategy, the proposed strategy doesn’t align all the channel ADCs with the reference ADC, but aligns channel ADCs with each other and remains a time interval with the reference ADC. The time interval is acceptable in a wide range. It can enhance the sensitivity of time skew detection. By using only the maximum significant bit of channel ADC output to calculate the autocorrelation value, hardware overhead can be further reduced. After time skew calibration, measurement results show that signal-to-noise and distortion ratio and interleaving spur are improved to 68.5 dB and −90.7 dBc from 68.0 dB and −76.0 dBc, respectively, at low input frequency, and to 66.1 dB and −77.9 dBc from 58.7 dB and −59.5 dBc, respectively, at Nyquist frequency. At Nyquist frequency, the proposed ADC achieves a Walden FOM of 0.9 pJ/conv.-step.