High-speed high-resolution low-power self-calibrated digital-to-analog converters

Abstract

High-speed and high-resolution low-power digital-to-analog converters (DACs) are basic design blocks in many applications. Several obvious conflicting requirements such as high-speed, high-resolution, low-power, and small-area have to be satisfied. In this dissertation, a modular architecture for continuous self-calibrating DACs is proposed to satisfy the above requirements. This includes a redundant-cell-relay continuous selfcalibration scheme. Several prototype DACs were implemented with self-calibration schemes. Also a DAC synthesis algorithm using a direct-mapping method and the modular structure was developed and implemented in the Cadence SKILL programming language. One of the prototypes is a 250MS/s 8-bit continuous self-calibrated DAC that has been implemented in TSMC's 0.25/x single poly five metal logic CMOS process. The structure of the self-calibrated current cell has high impedance and low sensitivity to output node voltage fluctuations. The chip has achieved 4-0.15/-0.1 LSB DNL, -0.6/4-0.4 LSB INL, and 55dB SFDR with a lower input frequency at a conversion rate of 250MS/s. It consumes 8 mW of power in a 0.13 mm2 die area. Glitches caused by switching of the calibration clock degrade the SFDR especially in high-speed applications. A new redundant-cell-relay continuous self-calibration scheme was proposed to reduce the glitches. Simulation results showed that the glitch energy is reduced 10 fold over existing schemes. A 10-bit DAC was implemented in the 0.25[i CMOS process mentioned above. 4-/-0.5 LSB INL and -0.45/4-0.2 LSB DNL were measured and 70dB SFDR was achieved with a lower input frequency at a 250MS/s