Abstract
A low dropout regulator(LDO) based on flipped voltage follower (FVF) assisted by a voltage combiner is presented in this work. This LDO offers stable regulation over wide range of load capacitances starting from 10pF to 50nF, without depending upon on-chip or off-chip load capacitance. It also offers extended the load regulation operation from 200µA to 50mA. This enhancement is achieved by incorporating a a voltage combiner stage, small feed-forward capacitor (C <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">F</inf> ) and compensation circuitry. For improving stability, Miller’s Compensation with a nulling resistor is implemented using 75pF capacitor, 4.5kΩ resistor. In addition, a slew rate enhancement circuit is applied to reduce the voltage undershoot during sharp load current transitions down to 200mV at 100pF. The designed LDO is verified with simulation in 45-nm CMOS process. For an input voltage of a 1.2V and output voltage of 1.08V, the simulated worst case undershoot and overshoot are respectively 115 mV and 74 mV, respectively, for load transient of 200µA to 50mA within edge times of 10 nSec. The quiescent current is 25uA. The simulated PSR is -42 dB over the band of 10-1kHz, -20dB at 1MHz over 200uA-50mA of load currents.
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