A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology

K Kanda ,Eiichi Makino,Dai Nakamura,Siu Lung Chan,Kazuhide Yoneya,Alex Mak,Koji Hosono,Takashi Taira,Masahiro Yoshihara,Raul Cernea,Binh Le,Yuya Suzuki,Norifumi Kajimura,T Hisada ,Shingo Miyamoto ,Shigefumi Fujimura ,M Koyanagi ,T Arizono ,Y Okukawa ,G Hemink ,Masayasu Kojima ,Toru Maruyama ,Takeshi Kamei ,T Yaegashi ,Frank C Tsai ,Fuminori Ito ,Yasuyuki Kato ,H Okada ,Takaki Miwa ,K Ino ,Yoshinori Takeuchi ,Masamitsu Itoh ,M Higashitani ,T Yamamura ,M Noguchi ,M Shirakawa ,S Ohshima

doi:10.1109/isscc.2008.4523241

Abstract

NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.

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