A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

Abstract

This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.