A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR

Abstract

In this paper, a 500 MSPS 8-bit segmented Current Steering Digital to Analog Converter (CS-DAC) with high dynamic and static performance is presented. This CS-DAC is designed using 180 nm CMOS technology for communication applications. To mitigate the tradeoff between area and performance, the proposed CS-DAC architecture follows 5+3 segmentation. The 5 MSB bits and 3 LSB bits are realized using unary DACs and binary DACs structure, respectively. For better linearity and matching, the unit current cells are biased with temperature and supply independent on-chip voltage reference circuit. The value of Spurious Free Dynamic Range (SFDR) of this DAC is > 66 dB up to 166.5 MHz signal frequency. The near Nyquist SFDR is >62 dB at 243 MHz signal frequency. The Integral Non-linearity (INL) and Dynamic Non-linearity (DNL) of the DAC are observed as 0.019 LSB and 0.026 LSB, respectively. The simulated power dissipation of this proposed DAC is 11.07 mW at 1.8 V supply voltage for 5.36 MHz input signal at 500 MSPS sampling frequency.