Design and analysis of 4-bit low-power, high-performance current steering DAC implemented using CNT-GDI logic

Abstract

This work proposes a 4-bit unary weighted current steering digital to analog converter (CS-DAC) with minimal integral nonlinearity (INL) error, less power consumption, and low glitch area. The input to the differential switch is through the thermometer decoder designed using GDI (Gate Input diffusion) logic, which lowers the power consumption and glitch area (also known as glitch energy) to 7.7nW and 0.0038 pVs respectively. Additionally, this unary decoder is used in the digital block of the proposed CS-DAC to lower the overall space and power consumption. The proposed circuitry employs 32 nm technology CNTFET technology. The comparative analysis of the CNTFET based proposed unary decoder design has shown a significant improvement of various performance measuring parameters. The power consumption, latency, and PDP has got substantially reduced by ∼94 %, ∼86 %, and ∼99 % in comparison to the conventional MOSFET based circuitry. In addition, it has been observed that in the proposed CNTFET GDI logic-based CS-DAC the INL, and differential non linearity (DNL) have got decreased by ∼89 % and ∼92 % respectively in comparison to the conventional MOS-based CS-DAC.Further, the dynamic performance measuring parameter like Spurious Free Dynamic Range (SFDR) has got increased by 41.7 % in comparison to the conventional CS-DAC. With a single 0.9 V supply voltage, the proposed DAC dissipates ∼100 % less power as compared to conventional CMOS-based CS-DAC.