A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology

P Delizia,S D'Amico,A Baschirotto,G Saccomanno

doi:10.1109/iscas.2010.5537644

P Delizia, S D'Amico + Show 2 more

https://doi.org/10.1109/iscas.2010.5537644

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In this paper the design of a 10b 100-MS/s pipeline analog-to-digital converter (ADC) with an optimized bit-stage resolution is presented. A careful analysis of the ADC architecture is presented. The proposed architecture is made by two main stages with opamp-sharing technique and a 3b full-flash ADC. The 1st stage has a 1.5b resolution architecture, the remaining stages have 2.5b resolution architecture. Furthermore, the input sampling is directly performed on the 1st stage. The ADC is implemented in 65nm digital CMOS process technology. It achieves 69.3dB spurious-free-dynamic-range (SFDR), 59.3dB signal-to-noise ratio (SNR), 9.6 effective number of bits (ENOB) for a 49MHz input at full sampling rate. The ADC power consumption is about 12.7mW from a 1.2V supply. The FOM value is about 165fJ/conv. It occupies 0.8mm2.

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