A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-$\mu $ m CMOS Technology

Abstract

This brief presents a zero-crossing-based pipeline analog-to-digital converter (ADC) architecture that can effectively reduce hardware complexity and power consumption for high-speed ADCs. The ADC uses only simple open-loop amplifiers for residue amplification. Using modified sliding interpolation and subranging techniques, the number of amplifiers is reduced by 60%. A 10-bit 200-MS/s ADC, employing the architecture and other techniques, such as double sampling, digital error correction, and source degeneration, is fabricated in 0.13- $\mu $ m CMOS process and occupies a die area of 0.7 $\mathrm{mm}^{2}$ . The differential and integral nonlinearity of the ADC are less than 0.83/−0.47 and 1.05/−0.7 LSB, respectively. With a 1.5-MHz full-scale input, the ADC achieves 56.5-dB signal-to-noise plus distortion ratio, 71.8-dB spurious free dynamic range, and 9.1 effective number of bits at full sampling rate while dissipating 38 mW from a 1.2-V supply.