A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-$g_{m}$ Opamp

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A pipelined analog-to-digital converter (ADC) architecture which is suitable for low power and small area is presented. The prototype ADC achieves 10-bit resolution with only two opamps by removing a front-end sample-and-hold amplifier (SHA) and sharing an opamp between two successive pipeline stages. The errors from the absence of SHA and opamp-sharing are greatly reduced by the proposed techniques and circuits. Further reduction of power and area is achieved by using a capacitor-sharing technique and variable-<formula formulatype="inline"> <tex Notation="TeX">$g_{m}$</tex></formula> opamp. The ADC is implemented in 0.18 <formula formulatype="inline"><tex Notation="TeX">$\mu\hbox{m}$</tex> </formula> CMOS technology and occupies a die area of 0.86 <formula formulatype="inline"> <tex Notation="TeX">${\hbox{mm}}^{2}$</tex></formula>. The differential and integral nonlinearity of the ADC are less than 0.39 LSB and 0.81 LSB, respectively, at full sampling rate. The ADC achieves 56.2 dB signal-to-noise plus distortion ratio, 72.7 dB spurious free dynamic range, <formula formulatype="inline"> <tex Notation="TeX">${-}$</tex></formula>66.2<formula formulatype="inline"> <tex Notation="TeX">$~$</tex></formula>dB total harmonic distortion, 9.03 effective number of bits for a Nyquist input at full sampling rate, and consumes 12 mW from a 1.8 V supply. </para>